Philips Semiconductors
Product specification
Stand-alone CAN controller
6.3.2
R
ESET VALUES
SJA1000
Detection of a ‘reset request’ results in aborting the current transmission/reception of a message and entering the reset
mode. On the ‘1-to-0’ transition of the reset request bit, the CAN controller returns to the operating mode.
Table 2
Reset mode configuration; notes 1 and 2
VALUE
SETTING
BIT CR.0 BY
SOFTWARE OR
DUE TO
BUS-OFF
0
X
1
X
X
X
X
1 (reset mode)
note 3
REGISTER
BIT
SYMBOL
NAME
RESET BY
HARDWARE
Control
CR.7
CR.6
CR.5
CR.4
CR.3
CR.2
CR.1
CR.0
−
−
−
OIE
EIE
TIE
RIE
RR
−
−
−
GTS
CDO
RRB
AT
TR
BS
ES
TS
RS
TCS
TBS
DOS
RBS
−
−
−
WUI
DOI
EI
TI
RI
reserved
reserved
reserved
Overrun Interrupt Enable
Error Interrupt Enable
Transmit Interrupt Enable
Receive Interrupt Enable
Reset Request
reserved
reserved
reserved
Go To Sleep
Clear Data Overrun
Release Receive Buffer
Abort Transmission
Transmission Request
Bus Status
Error Status
Transmit Status
Receive Status
Transmission Complete Status
Transmit Buffer Status
Data Overrun Status
Receive Buffer Status
reserved
reserved
reserved
Wake-Up Interrupt
Data Overrun Interrupt
Error Interrupt
Transmit Interrupt
Receive Interrupt
10
0
X
1
X
X
X
X
1 (reset mode)
note 3
Command
CMR.7
CMR.6
CMR.5
CMR.4
CMR.3
CMR.2
CMR.1
CMR.0
Status
SR.7
SR.6
SR.5
SR.4
SR.3
SR.2
SR.1
SR.0
0 (bus-on)
0 (ok)
0 (idle)
0 (idle)
1 (complete)
1 (released)
0 (absent)
0 (empty)
1
1
1
0 (reset)
0 (reset)
0 (reset)
0 (reset)
0 (reset)
X
X
0 (idle)
0 (idle)
X
1 (released)
0 (absent)
0 (empty)
1
1
1
0 (reset)
0 (reset)
X; note 4
0 (reset)
0 (reset)
Interrupt
IR.7
IR.6
IR.5
IR.4
IR.3
IR.2
IR.1
IR.0
2000 Jan 04
PHILIPS [ NXP SEMICONDUCTORS ]
