Philips Semiconductors
Product specification
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
SCC2698B
Table 5. Baud Rates Extended
Normal BRG
BRG Test
CSR[7:4]
0000
0001
0010
0011
0100
0101
0110
0111
ACR[7] = 0
50
ACR[7] = 1
75
ACR[7] = 0
4,800
ACR[7] = 1
7,200
110
110
880
880
134.5
200
38.4K
150
1,076
38.4K
19.2K
14.4K
300
300
28.8K
28.8K
600
600
57.6K
57.6K
1,200
1,050
2,400
4,800
7,200
9,600
38.4K
Timer
I/O2 – 16X
I/O2 – 1X
1,200
2,000
2,400
4,800
1,800
9,600
19.2K
Timer
I/O2 – 16X
I/O2 – 1X
115.2K
1,050
115.2K
2,000
1000
1001
1010
1011
1100
1101
1110
57.6K
57.6K
4,800
4,800
57.6K
14.4K
9,600
9,600
38.4K
19.2K
Timer
Timer
I/O2 – 16X
I/O2 – 1X
I/O2 – 16X
I/O2 – 1X
1111
NOTE:
Each read on address H‘2’ will toggle the baud rate test mode. When in the BRG test mode, the baud rates change as shown to the left. This
change affects all receivers and transmitters on the DUART.
The test mode at address H‘A’ changes all transmitters and receivers to the 1x mode and connects the output ports to some internal nodes.
A condition that occurs infrequently has been observed where the receiver will ignore all data. It is caused by a corruption of the start bit
generally due to noise. When this occurs the receiver will appear to be asleep or locked up. The receiver must be reset for the UART to
continue to function properly.
Reset in the Normal Mode (Receiver Enabled)
Recovery can be accomplished easily by issuing a receiver software reset followed by a receiver enable. All receiver data, status and
programming will be preserved and available before reset. The reset will NOT affect the programming.
Reset in the Wake-Up Mode (MR1[4:3] = 11)
Recovery can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software
reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and available before
reset. The reset will NOT affect the programming.
The receiver has a digital filter designed to reject “noisy” data transitions and the receiver state machine was designed to reject noisy start
bits or noise that might be considered a start bit. In spite of these precautions, corruption of the start bit can occur in 15ns window
–5
approximately 100ns prior to the rising edge of the data clock. The probability of this occurring is less than 10 at 9600 baud.
A corrupted start bit may have some deleterious effects in ASYNC operation if it occurs within a normal data block. The receiver will tend
to align its data clock to the next ‘0’ bit in the data stream, thus potentially corrupting the remainder of the data block. A good design
practice, in environments where start bit corruption is possible, is to monitor data quality (framing error, parity error, break change and
received break) and “data stopped” time out periods. Time out periods can be enabled using the counter/timer in the SCC2691, SCC2692,
SCC2698B and SC68692 products. This monitoring can indicate a potential start bit corruption problem.
SD00097
26
2000 Jan 31
NXP [ NXP ]
