Philips Semiconductors
Product specification
Dual universal asynchronous receiver/transmitter (DUART)
SC26C92
V
CC
= 5V
±
10%, T
A
= –40_C to 85_C, unless otherwise specified.
SYMBOL
PARAMETER
Reset Timing (See Figure 3)
t
RES
RESET pulse width
5
(See Figure 4)
Bus Timing
t
AS
A0-A3 setup time to RDN, WRN Low
t
AH
A0-A3 hold time from RDN, WRN Low
t
CS
CEN setup time to RDN, WRN Low
t
CH
CEN hold time from RDN, WRN High
t
RW
WRN, RDN pulse width
t
DD
Data valid after RDN Low
t
DF
Data bus floating after RDN High
t
DS
Data setup time before WRN or CEN High
t
DH
Data hold time after WRN or CEN High
t
RWD
High time between reads and/or writes
5, 6
Port Timing
5
(See Figure 5)
t
PS
Port input setup time before RDN Low
t
PH
Port input hold time after RDN High
t
PD
OP
n
output valid from WRN High
Interrupt Timing (See Figure 6)
INTRN (or OP3-OP7 when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
t
IR
Reset command (break change interrupt)
Stop C/T command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
Clock Timing (See Figure 7)
t
CLK
X1/CLK High or Low time
f
CLK
X1/CLK frequency
t
CTC
CTCLK (IP2) High or Low time
f
CTC
CTCLK (IP2) frequency
t
RX
RxC High or Low time (16X)
f
RX
RxC frequency (16X)
(1X)
8
t
TX
TxC High or Low time (16X)
f
TX
TxC frequency (16X)
(1X)
8
Min
200
10
25
0
0
70
55
25
25
0
30
0
0
100
LIMITS
Typ
3
Max
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC CHARACTERISTICS
1, 2, 4
100
100
100
100
100
100
50
0.1
55
0
30
0
0
30
0
0
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
3.6864
8
8
16
1
16
1
Transmitter Timing (See Figure 8)
t
TXD
TxD output delay from TxC external clock input on IP pin
60
ns
t
TCS
Output delay from TxC low at OP pin to TxD data output
5
30
ns
Receiver Timing (See Figure 9)
t
RXS
RxD data setup time before RxC high at external clock input on IP pin
50
ns
t
RXH
RxD data hold time after RxC high at external clock input on IP pin
50
ns
NOTES:
1. Parameters are valid over specified temperature range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 3.0V with a transition time of 5ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of 0.8V and 2.0V and
output voltages of 0.8V and 2.0V, as appropriate.
3. Typical values are at +25°C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50pF, R
L
= 2.7KΩ to V
CC
.
5. Timing is illustrated and referenced to the WRN and RDN inputs. Also, CEN may be the ‘strobing’ input. CEN and RDN (also CEN and
WRN) are ORed internally. The signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum High times between one CEN and the next. The RDN signal must
be negated for t
RWD
to guarantee that any status register changes are valid.
7. Minimum frequencies are not tested but are guaranteed by design. Crystal frequencies 2 to 4 MHz.
8. Clocks for 1X mode should be symmetrical.
2000 Jan 31
7
PHILIPS [ NXP SEMICONDUCTORS ]
