Philips Semiconductors
Preliminary specification
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb filter, VBI-data slicer and high performance scaler
SAA7114H
In Tables 12 and 13 PHO is a usable common phase
offset.
The registers are assigned to the following events;
e.g. subaddresses B8H to BBH:
• B8H: 00 = input field ID 0, task status bit 0 (toggle
status, see Section 8.3.1.3)
Please notice that the equations of Fig.29 are producing
an interpolated output also for the unscaled case, as the
geometrical reference position for all conversions is the
position of the first line of the lower field (see Table 12).
• B9H: 01 = input field ID 0, task status bit 1
• BAH: 10 = input field ID 1, task status bit 0
• BBH: 11 = input field ID 1, task status bit 1.
If there is no need for UP-LO and LO-UP conversion and
the input field ID is the reference for the back-end
operation, then it is UP-LO = UP-UP and LO-UP = LO-LO
and the 1⁄2 line phase shift (PHO + 16) can be skipped.
This case is listed in Table 13.
Dependent on the input signal (interlaced or
non-interlaced) and the task processing (50 Hz or field
reduced processing with one or two tasks, see examples
in Section 8.3.1.3), also other combinations may be
possible, but the basic equations are the same.
The SAA7114H supports 4 phase offset registers per task
and component (luminance and chrominance). The value
of 20H represents a phase shift of one line.
Table 12 Examples for vertical phase offset usage: global equations
INPUT FIELD UNDER
PROCESSING
OUTPUT FIELD
INTERPRETED AS
EQUATION FOR PHASE OFFSET
CALCULATION (DECIMAL VALUES)
USED ABBREVIATION
Upper input lines
Upper input lines
upper output lines
lower output lines
UP-UP
UP-LO
PHO + 16
YSCY[15:0]
------------------------------
64
PHO +
PHO
+ 16
Lower input lines
Lower input lines
upper output lines
LO-UP
Lower output lines LO-LO
YSCY[15:0]
------------------------------
64
PHO +
2000 Mar 15
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