Philips Semiconductors
SAA7113H
9-bit video input processor
8.2.1 Clamping
The clamp control circuit controls the correct clamping of the analog input signals. The
coupling capacitor is also used to store and filter the clamping voltage. An internal digital
clamp comparator generates the information with respect to clamp-up or clamp-down.
The clamping levels for the two ADC channels are fixed for luminance (120) and
chrominance (256). Clamping time in normal use is set with the HCL pulse on the back
porch of the video signal.
8.2.2 Gain control
The gain control circuit receives (via the I
2
C-bus) the static gain levels for the two analog
amplifiers or controls one of these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO). The AGC for luminance is used
to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input
voltage range. The AGC active time is the sync bottom of the video signal.
Signal (white) peak control limits the gain at signal overshoots. The flow charts
(see
and
show more details of the AGC. The influence of supply
voltage variation within the specified range is automatically eliminated by clamp and
automatic gain control.
TV line
analog line blanking
255
GAIN
60
1
CLAMP
HCL
HSY
mgl065
Fig 4. Analog line with clamp (HCL) and gain range (HSY)
analog input level
+3
dB
0 dB
(1 V (p-p) 18/56
Ω)
−6
dB
minimum
maximum
controlled
ADC input level
range 9 dB
0 dB
mhb325
Fig 5. Automatic gain range
9397 750 14232
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 9 May 2005
8 of 75
PHILIPS [ NXP SEMICONDUCTORS ]
