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SAA7113H/V1 参数 Datasheet PDF下载

SAA7113H/V1图片预览
型号: SAA7113H/V1
PDF下载: 下载PDF文件 查看货源
内容描述: [IC SPECIALTY CONSUMER CIRCUIT, PQFP44, PLASTIC, SOT-307, QFP-44, Consumer IC:Other]
分类和应用: 商用集成电路
文件页数/大小: 87 页 / 440 K
品牌: NXP [ NXP ]
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Table 17 Sliced data format on the 8-bit VPO-bus (data types 0 to 5 and 8 to 14)  
BLANKING  
PERIOD  
TIMING  
REFERENCE CODE  
TIMING  
REFERENCE CODE  
BLANKING  
PERIOD  
INTERNAL HEADER  
DC IDI1 IDI2 DLN1  
SLICED DATA  
DHN1 ... DLNn  
... 80 10 FF 00 00 SAV SDID  
DHNn  
FF 00 00 EAV 80 10 ...  
Table 18 Explanation to Table 17  
NAME  
EXPLANATION  
SAV  
start of active data; see Tables 5 to 7  
SDID sliced data identification: NEP(1), EP(2), SDID5 to SDID0, freely programmable via I2C-bus subaddress 5EH, D5 to D0, e. g. to be used as  
source identifier  
DC  
Dword count: NEP(1), EP(2), DC5 to DC0; DC is inserted for software compatibility reasons to SAA7112, but does not represent any relevant  
information for SAA7113H applications.  
DC describes the number of succeeding 32-bit words:  
DC = 14(C + n), where C = 2 (the two data identification bytes IDI1 and IDI2) and n = number of decoded bytes according to the chosen text  
standard. As the sliced data are transmitted nibble wise, the maximum number of bytes transmitted (NBT) starting at IDI1 results to:  
NBS = (DC × 8) 2  
DC can vary between 1 and 11, depending on the selected data type.  
Note that the number of bytes actually transmitted can be less than NBT for two reasons:  
1. result of DC would result to a non-integer value (DC is always rounded up)  
2. standard not recognized (wrong standard or poor input signal)  
IDI1  
IDI2  
internal data identification 1: OP(3), FID (field 1 = 0, field 2 = 1), LineNumber8 to LineNumber3  
internal data identification 2: OP(3), LineNumber2 to LineNumber0, DataType3 to DataType0; see Table 4  
DLNn sliced data LOW nibble, format: NEP(1), EP(2), D3 to D0, 1, 1  
DLHn sliced data HIGH nibble, format: NEP(1), EP(2), D7 to D4, 1, 1  
EAV  
end of active data; see Tables 5 to 7  
Notes  
1. Inverted EP (bit 7); for EP see note 2.  
2. Even parity (bit 6) of bits 5 to 0.  
3. Odd parity (bit 7) of bits 6 to 0.  
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