Philips Semiconductors
Product specification
Enhanced Video Input Processor (EVIP)
7
PINNING
PIN
SYMBOL
(L)QFP64
n.c.
TDO
TDI
TMS
V
SSA2
AI22
V
DDA2
AI21
V
SSA1
AI12
V
DDA1
AI11
V
SSS
AOUT
V
DDA0
V
SSA0
VREF
V
DDD5
V
SSD5
LLC
LLC2
CREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
−
O
I
I
P
I
P
I
P
I
P
I
P
O
P
P
O
P
P
O
O
O
Do not connect.
Test data output for boundary scan test; note 1.
Test data input for boundary scan test; note 1.
Test mode select input for boundary scan test or scan test; note 1.
Ground for analog supply voltage channel 2.
Analog input 22.
Positive supply voltage for analog channel 2 (+3.3 V).
Analog input 21.
Ground for analog supply voltage channel 1.
Analog input 12.
Positive supply voltage for analog channel 1 (+3.3 V).
Analog input 11.
Substrate ground connection.
Analog test output; for testing the analog input channels.
I/O/P
DESCRIPTION
SAA7111A
Positive supply voltage for internal Clock Generator Circuit (CGC) (+3.3 V).
Ground for internal CGC.
Vertical reference output signal (I
2
C-bit COMPO = 0) or inverse composite blanking
signal (I
2
C-bit COMPO = 1) (enabled via I
2
C-bus bit OEHV).
Digital supply voltage 5 (+3.3 V).
Ground for digital supply voltage 5.
Line-locked system clock output (27 MHz).
Line-locked clock
1
⁄
2
output (13.5 MHz).
Clock reference output: this is a clock qualifier signal distributed by the internal CGC
for a data rate of LLC2. Using CREF all interfaces on the VPO bus are able to
generate a bus timing with identical phase. If CCIR 656 format is selected
(OFTS0 = 1 and OFTS1 = 1) an inverse composite blanking signal (pixel qualifier) is
provided on this pin.
Reset output (active LOW); sets the device into a defined state. All data outputs are
in high impedance state. The I
2
C-bus is reset (waiting for start condition).
Chip enable; connection to ground forces a reset, up from version 3 power save
function additionally available.
Digital supply voltage input 4 (+3.3 V).
Ground for digital supply voltage input 4.
Horizontal sync output signal (programmable); the positions of the positive and
negative slopes are programmable in 8 LLC increments over a complete line
(equals 64
µs)
via I
2
C-bus bytes HSB and HSS. Fine position adjustment in 2 LLC
increments can be performed via I
2
C-bus bits HDEL1 and HDEL0.
Two functions output; controlled by I
2
C-bus bit RTSE1.
RTSE1 = 0: PAL line identifier (LOW = PAL line); indicates the inverted and
non-inverted R
−
Y component for PAL signals. RTSE1 = 1: H-PLL locked indicator;
a high state indicates that the internal horizontal PLL has locked.
6
RES
CE
V
DDD4
V
SSD4
HS
23
24
25
26
27
O
I
P
P
O
RTS1
28
O
1998 May 15
PHILIPS [ NXP SEMICONDUCTORS ]
