Philips Semiconductors
Product specification
Radio Data System (RDS) demodulator
SAA6579
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); ground pins 6 and 11 connected together.
SYMBOL
V
DDA
V
DDD
V
n
T
stg
T
amb
V
es
PARAMETER
analog supply voltage (pin 5)
digital supply voltage (pin 12)
voltage on all pins; grounds excluded
storage temperature
operating ambient temperature
electrostatic handling for all pins except
pins 9 and 10
note 1
note 2
CONDITIONS
0
0
−0.5
−40
−40
±300
+1500
MIN.
6
6
V
DDX
+ 0.5
+150
+85
−
−3000
MAX.
V
V
V
°C
°C
V
V
UNIT
Notes
1. Equivalent to discharging a 200 pF capacitor via a 0
Ω
series resistor.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
FUNCTIONAL DESCRIPTION
The SAA6579 is a demodulator circuit for RDS
applications. It contains a 57 kHz bandpass filter and a
digital demodulator to regenerate the RDS data stream out
of the multiplex signal (MPX).
Filter part
The MUX signal is band-limited by a second-order
anti-aliasing-filter and fed through a 57 kHz band-pass
filter (8th order band-pass filter with 3 kHz bandwidth) to
separate the RDS signals. This filter uses switched
capacitor technique and is clocked by a clock frequency of
541.5 kHz derived from the 4.332/8.664 MHz crystal
oscillator. Then the signal is fed to the reconstruction filter
to smooth the sampled and filtered RDS signal before it is
output on pin 8. The signal is AC-coupled to the
comparator (pin 7). The comparator is clocked with a
frequency of 228 kHz (synchronized by the 57 kHz of the
demodulator).
Digital part
The synchronous demodulator (Costas loop circuit) with
carrier regeneration demodulates the internal coupled,
digitized signal. The suppressed carrier is recovered from
the two sidebands (Costas loop). The demodulated signal
is low-pass-filtered in such a way that the overall pulse
shape (transmitter and receiver) approaches a
cosinusoidal form in conjunction with the following
Integrate and dump circuit.
The data-spectrum shaping is split into two equal parts and
handled in the transmitter and in the receiver. Ideally, the
data filtering should be equal in both of these parts.
The overall data-channel-spectrum shaping of the
transmitter and the receiver is approximately 100% roll-off.
The Integrate and dump circuit performs an integration
over a clock period. This results in a demodulated and
valid RDS signal in form of biphase symbols being output
from the integrate and dump circuit. The final stages of
RDS data processing are the biphase symbol decoding
and the differential decoding. After synchronization by
data clock RDCL (pin 16) data appears on the RDDA
output (pin 2). The output of the biphase symbol decoder
is evaluated by a special circuit to provide an indication of
good data (QUAL = HIGH) or corrupt data (QUAL = LOW).
Timing
Fixed and variable dividers are applied to the
4.332/8.664 MHz crystal oscillator to generate the
1.1875 kHz RDS clock RDCL, which is synchronized by
the incoming data. Which ever clock edge is considered
(positive or negative going edge) the data will remain valid
for 399
µs
after the clock transition. The timing of data
change is 4
µs
before a clock change. Which clock
transition (positive or negative going clock) the data
change occurs in, depends on the lock conditions and is
arbitrary (bit slip).
During poor reception it is possible that faults in phase
occur, then the clock signal stays uninterrupted, and data
is constant for 1.5 clock periods. Normally, faults in phase
do not occur on a cyclic basis. If however, faults in phase
occur in this way, the minimum spacing between two
possible faults in phase depends on the data being
transmitted. The minimum spacing cannot be less than
16 clock periods. The quality bit changes only at the time
of a data change.
5
1997 Feb 24
PHILIPS [ NXP SEMICONDUCTORS ]
