Philips Semiconductors
Preliminary specification
1394 enhanced AV link layer controller
PDI1394L40
5.0 PIN CONFIGURATION
144
109
1
108
LQFP
36
73
37
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Function
HIF D15
HIF D14
HIF D13
HIF D12
GND
V
DD
HIF D11
HIF D10
HIF D9
HIF D8
GND
V
DD
HIF AD7
HIF AD6
HIF AD5
HIF AD4
GND
V
DD
HIF AD3
HIF AD2
HIF AD1
HIF AD0
GND
V
DD
HIF A8
HIF A7
HIF A6
HIF A5
HIF A4
HIF A3
HIF A2
HIF A1
HIF A0
GND
V
DD
HIF CSN
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Function
HIF WRN
HIF INTN
HIF ALE
HIF RDN
HIF WAIT
RESETN
GND
V
DD
HIF 16BIT
HIF MUX
1394 MODE
PD
RESERVED
RESERVED
RESERVED
RESERVED
GND
V
DD
CLK50
CYCLEIN
CYCLEOUT
RESERVED
RESERVED
GND
V
DD
TESTPIN
TESTPIN
TESTPIN
RESERVED
RESERVED
RESERVED
RESERVED
GND
V
DD
RESERVED
RESERVED
Pin
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
72
Function
PHY D7*
PHY D6*
PHY D5*
PHY D4*
GND
V
DD
PHY D3*
PHY D2*
PHY D1*
PHY D0*
GND
V
DD
PHY CTL1*
PHY CTL0*
LREQ
SCLK*
GND
V
DD
LPS*
LINKON
ISON
GND
V
DD
AV1ERR0
AV1ERR1
AV1ENDPCK
AV1CLK
AV1FSYNC
AV1 SY
AV1VALID
AV1SYNC
RESERVED
RESERVED
GND
V
DD
AV1D0
Pin
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Function
AV1D1
AV1D2
AV1D3
GND
V
DD
AV1D4
AV1D5
AV1D6
AV1D7
AV1READY
GND
V
DD
AV2ERR0/LTLEND
AV2ERR1/DATINV
AV2ENDPCK
AV2CLK
AV2FSYNC
AV2 SY
AV2VALID
AV2SYNC
RESERVED
RESERVED
GND
V
DD
AV2D0
AV2D1
AV2D2
AV2D3
GND
V
DD
AV2D4
AV2D5
AV2D6
AV2D7
AV2READY
RESERVED
*
Indicates pin equipped with internal bus hold circuit activated by the state of the ISON pin.
SV01832
2000 Dec 15
2
PHILIPS [ NXP SEMICONDUCTORS ]
