Philips Semiconductors
Preliminary specification
1394 enhanced AV link layer controller
PDI1394L40
9.4 Phy Interface
PIN No.
82, 81, 80, 79,
76, 75, 74, 73
86, 85
47
87
88
91
92
PIN SYMBOL
PHY D[0:7]
PHY CTL[0:1]
1394 MODE
LREQ
SCLK
LPS
LINKON
I/O
I/O
I/O
I
O
I
O
I
NAME AND FUNCTION
Data 0 (MSB) through 7 (NOTE: To preserve compatibility to the specified Link-Phy interface of
the IEEE 1394–1995 standard, Annex J, bit 0 is the most significant bit). Data is expected on
AV D[0:1] for 100Mb/s, AV D[0:3] for 200Mb/s, and AV D[0:7] for 400Mb/s. See IEEE 1394–1995
standard, Annex J for more information.
Control Lines between Link and Phy. See 1394 Specification for more information.
1394–1995 Annex J PHY (HIGH), or 1394a PHY (LOW)
Link Request. Bus request to access the PHY. See IEEE 1394–1995 standard, Annex J for more
information. (Used to request arbitration or read/write PHY registers).
System clock. 49.152MHz input from the PHY (the PHY-LINK interface operates at this frequency).
Link power status. Outputs a frequency (typically 1.4 MHz) with 25% duty cycle which tells the PHY
chip that the L40 is active.
L40 generates a host interrupt when this pin receives a link on signal from the PHY. Interrupt is a
request from another node for the L40 to be powered up (see PD pin).
Isolation mode. This pin is asserted (LOW) when an Annex J type isolation barrier is used.
See IEEE 1394–1995 Annex J. for more information. When tied HIGH, this pin enables internal
bushold circuitry on the affected PHY interface pins (see below). Active bushold circuits allow
either the direct connection to PHY pins or the use of the single capacitor isolation mode.
93
ISON
I
9.5 Other Pins
PIN No.
5, 11, 17, 23,
34, 43, 53, 60,
69, 77, 83, 89,
94, 106, 112,
119, 131, 137
6, 12, 18, 24,
35, 44, 54, 61,
70, 78, 84, 90,
95, 107, 113,
120, 132, 138
48
49, 50, 51, 52,
58, 59, 65, 66,
67, 68, 71, 72
104, 105, 129,
130, 144
55
56
57
62, 63, 64
PIN SYMBOL
I/O
NAME AND FUNCTION
GND
Ground reference
V
DD
3.3 V
±
0.3 V power supply
PD
1,2,3,4
I
Power Down. When asserted (high), the AV Link goes into a low power mode and de-asserts the
LPS pin. When in this state, reads and writes to the registers are not allowed. The AV Link will
resume operation when PD is de-asserted (low), all register settings and configurations are
restored to their pre power down values.
These pins are reserved for factory testing. For normal operation they should be connected to
ground.
Auxiliary clock, value is SCLK (usually 49.152 MHz)
Provides the capability to supply an external cycle timer signal for the beginning of 1394 bus
cycles.
Reproduces the 8kHz cycle clock of the cycle master.
Test pins. These signals must be connected to ground.
RESERVED
NA
CLK50
CYCLEIN
CYCLEOUT
TESTPIN
O
I
O
NOTES:
Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in the following state of operation:
1. The isochronous transmit FIFO is not receiving data for transmission
2. The isochronous transmitter is disabled
3. No asynchronous packets are being generated for transmission
4. Both the ASYNC request and response queues are empty
2000 Dec 15
7
PHILIPS [ NXP SEMICONDUCTORS ]
