Philips Semiconductors
Product specification
LCD direct/duplex driver with
I
2
C-bus interface
6.7
Power-on reset
6.9
I
2
C-bus protocol
PCF8577C
At power-on reset the PCF8577C resets to a defined
starting condition as follows:
1. Both backplane outputs are set to V
SS
in master mode;
to 3-state in cascade mode
2. All segment outputs are set to V
SS
3. The segment byte registers and control register are
cleared
4. The I
2
C-bus interface is initialized.
6.8
Slave address
The PCF8577C I
2
C-bus protocol is shown in Fig.7.
The PCF8577C is a slave receiver and has a fixed slave
address (see Fig.6). All PCF8577Cs with the same slave
address acknowledge the slave address in parallel.
The second byte is always the control byte and is loaded
into the control register of each PCF8577C connected to
the I
2
C-bus. All addressed devices acknowledge the
control byte. Subsequent data bytes are loaded into the
segment registers of the selected device. Any number of
data bytes may be loaded in one transfer and in an
expanded system rollover of the SBV from 111 111 to
000 000 is allowed. If a stop (P) condition is given after the
control byte acknowledge the segment data will remain
unchanged. This allows the BANK bit to be toggled without
changing the segment register contents. During loading of
segment data only the selected PCF8577C gives an
acknowledge. Loading is terminated by generating a stop
(P) condition.
The PCF8577C slave address is shown in Fig.6.
Before any data is transmitted on the I
2
C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure.
S
0 1 1 1 0 1 0 0
SLAVE ADDRESS
A
MGA731
Fig.6 PCF8577C slave address.
acknowledge by
all PCF8577C
acknowledge by
all PCF8577C
msb
acknowledge by
selected PCF8577C only
lsb
MODE
BANK
S
SLAVE ADDRESS
0 A
SEGMENT
BYTE VECTOR
control byte
A
SEGMENT DATA
A
P
n bytes
R/W
MGA732
auto increment
segment byte vector
Fig.7 I
2
C-bus protocol.
1998 Jul 30
8
PHILIPS [ NXP SEMICONDUCTORS ]
