Philips Semiconductors
Product specification
Remote 16-bit I/O expander for I2C-bus
PCF8575
11 I2C-BUS TIMING CHARACTERISTICS
See Fig.13 and note 1.
SYMBOL
fSCL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
kHz
SCL clock frequency
−
400
50
−
tSW
tolerable spike width on bus
note 2
−
ns
tBUF
BUS free time between a STOP
and START condition
1.3
µs
tSU;STA
tHD;STA
tLOW
tHIGH
tr
START condition set-up time
START condition hold time
SCL LOW time
0.6
0.6
1.3
0.6
−
µs
µs
µs
µs
ns
ns
ns
ns
µs
pF
−
−
SCL HIGH time
−
SCL and SDA rise time
SCL and SDA fall time
data set-up time
note 3
note 3
20 + 0.1Cb
300
300
−
tf
20 + 0.1Cb
tSU;DAT
tHD;DAT
tSU;STO
Cb
100
0
data hold time
−
STOP condition set-up time
0.6
−
−
capacitive load represented by
each bus line
400
Notes
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL
and VIH with an input voltage swing of VSS to VDD
2. The device inputs SDA and SCL are filtered and will reject spikes on the bus lines of widths less than tSW(max)
.
.
3. The rise and fall times specified here refer to the driver device (PCF8575) and are part of the general fast I2C-bus
specification when PCF8575 asserts an acknowledge on SDA, the minimum fall time is 20 ns + 0.1Cb.
handbook, full pagewidth
START
CONDITION
(S)
BIT 7
MSB
(A7)
BIT 6
(A6)
BIT 0
LSB
(R/W)
ACKNOWLEDGE
(A)
STOP
CONDITION
(P)
PROTOCOL
t
t
t
LOW
HIGH
SU;STA
1/f
SCL
SCL
SDA
t
t
t
f
BUF
r
t
t
HD;DAT
t
t
HD;STA
SU;DAT
SU;STO
MGL546
Fig.13 I2C-bus timing diagram.
15
1999 Apr 07
NXP [ NXP ]
