NXP Semiconductors
PCF8566
Universal LCD driver for low multiplex rates
S8
S7
S6
25
24
23
22
S5
21
20
19
18
17
16
15
BP1
BP2
BP0
V
LCD
S9
S10
S11
S12
S13
S14
S15
S16
S17
S18
26
27
28
29
30
31
32
33
34
35
36
S19
37
S20
38
S21
39
S22
40
S23
1
SDA
2
SCL
3
SYNC
4
CLK
BP3
14
13
12
S2
S4
S3
S1
S0
PCF8566U
11
10
9
8
7
6
5
V
DD
V
SS
SA0
A2
A1
A0
OSC
mbh783
Fig 3. Pin configuration for PCF8566U
6.2 Pin description
Table 3.
Symbol
SDA
SCL
SYNC
CLK
V
DD
OSC
A0
A1
A2
SA0
V
SS
V
LCD
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
I
2
C-bus slave address bit 0 input
logic ground
LCD supply voltage
Description
I
2
C-bus data input and output
I
2
C-bus clock input and output
cascade synchronization input and output
external clock input and output
positive supply voltage
oscillator select
I
2
C-bus subaddress inputs
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
5 of 48
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