PCF8566
NXP Semiconductors
Universal LCD driver for low multiplex rates
V
DD
t
rise
R ≤
2 C
bus
V
V
LCD
DD
5
12
SDA
HOST
MICRO-
1
2
6
17 to 40 24 segment drives
LCD PANEL
SCL
PCF8566
PROCESSOR/
MICRO-
CONTROLLER
(up to 96
elements)
OSC
4 backplanes
13 to 16
10 11
7
8
9
mgg385
A0 A1 A2 SA0 V
SS
V
SS
Fig 4. Typical system configuration
7.1 Power-on reset
At power-on the PCF8566 resets to the following starting conditions:
• All backplane outputs are set to VDD
• All segment outputs are set to VDD
• Drive mode 1:4 multiplex with 1⁄3 bias is selected
• Blinking is switched off
• Input and output bank selectors are reset (as defined in Table 8)
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared
Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset
action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (Voper) is obtained from VDD − VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a 1⁄2 bias voltage level for the 1:2 multiplex
configuration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by
mode-set commands from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D), are given in Table 5.
PCF8566_7
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 07 — 25 February 2009
7 of 48
NXP [ NXP ]
