Philips Semiconductors
PCF8563
Real-time clock/calendar
8.4 Reset
The PCF8563 includes an internal reset circuit which is active whenever the oscillator
is stopped. In the reset state the I
2
C-bus logic is initialized and all registers, including
the address pointer, are cleared with the exception of bits FE, VL, TD1, TD0, TESTC
and AE which are set to logic 1.
8.5 Voltage-low detector and clock monitor
The PCF8563 has an on-chip voltage-low detector. When V
DD
drops below V
low
the
VL bit (Voltage Low, bit 7 in the Seconds register) is set to indicate that reliable
clock/calendar information is no longer guaranteed. The VL flag can only be cleared
by software.
The VL bit is intended to detect the situation when V
DD
is decreasing slowly for
example under battery operation. Should V
DD
reach V
low
before power is re-asserted
then the VL bit will be set. This will indicate that the time may be corrupted.
handbook, halfpage
MGR887
VDD
normal power
operation
period of battery
operation
Vlow
t
VL set
Fig 4. Voltage-low detection.
8.6 Register organization
Table 4: Registers overview
Bit positions labelled as ‘
−
’are not implemented; those labelled with ‘0’ should always be written with logic 0.
Address Register name
00H
01H
0DH
0EH
0FH
Control/Status 1
Control/Status 2
CLKOUT frequency
Timer control
Timer countdown
value
Bit 7
TEST1
0
FE
TE
Bit 6
0
0
−
−
Bit 5
STOP
0
−
−
Bit 4
0
TI/TP
−
−
Bit 3
TESTC
AF
−
−
Bit 2
0
TF
−
−
Bit 1
0
AIE
FD1
TD1
Bit 0
0
TIE
FD0
TD0
<timer countdown value>
9397 750 04855
© Philips Electronics N.V. 1999. All rights reserved.
Product specification
16 April 1999
5 of 30
PHILIPS [ NXP SEMICONDUCTORS ]
