NXP Semiconductors
P89V51RB2/RC2/RD2
8-bit microcontrollers with 80C51 core
Table 3.
Symbol
P2.5/A13
P2.6/A14
P2.7/A15
P89V51RB2/RC2/RD2 pin description
…continued
Pin
DIP40
26
27
28
TQFP44
23
24
25
PLCC44
29
30
31
I/O
O
I/O
O
I/O
O
I/O with
internal
pull-up
P2.5 —
Port 2 bit 5.
A13 —
Address bit 13.
P2.6 —
Port 2 bit 6.
A14 —
Address bit 14.
P2.7 —
Port 2 bit 7.
A15 —
Address bit 15.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins are pulled HIGH by the internal
pull-ups when ‘1’s are written to them and can be used as
inputs in this state. As inputs, Port 3 pins that are
externally pulled LOW will source current (I
IL
) because of
the internal pull-ups. Port 3 also receives some control
signals and a partial of high-order address bits during the
external host mode programming and verification.
P3.0 —
Port 3 bit 0.
RXD —
Serial input port.
P3.1 —
Port 3 bit 1.
TXD —
Serial output port.
P3.2 —
Port 3 bit 2.
INT0 —
External interrupt 0 input.
P3.3 —
Port 3 bit 3.
INT1 —
External interrupt 1 input.
P3.4 —
Port 3 bit 4.
T0 —
External count input to Timer/counter 0.
P3.5 —
Port 3 bit 5.
T1 —
External count input to Timer/counter 1.
P3.6 —
Port 3 bit 6.
WR —
External data memory write strobe.
P3.7 —
Port 3 bit 7.
RD —
External data memory read strobe.
Program Store Enable:
PSEN is the read strobe for
external program memory. When the device is executing
from internal program memory, PSEN is inactive (HIGH).
When the device is executing code from external program
memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each
access to external data memory. A forced HIGH-to-LOW
input transition on the PSEN pin while the RST input is
continually held HIGH for more than 10 machine cycles will
cause the device to enter external host mode
programming.
Type
Description
P3.0 to P3.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
PSEN
10
11
12
13
14
15
16
17
29
5
7
8
9
10
11
12
13
26
11
13
14
15
16
17
18
19
32
I
I
O
O
I
I
I
I
I/O
I
I/O
I
O
O
O
O
I/O
P89V51RB2_RC2_RD2_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 12 November 2009
8 of 80
PHILIPS [ NXP SEMICONDUCTORS ]
