Philips Semiconductors
Preliminary data
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
87LPC764
SPECIAL FUNCTION REGISTERS
Bit Functions and Addresses
SFR
Address
Reset
Value
Name
Description
MSB
LSB
E7
E6
E5
E4
E3
E2
E1
E0
ACC*
Accumulator
E0h
A2h
00h
1
AUXR1#
Auxiliary Function Register
KBF
F7
BOD
F6
BOI
F5
LPEP
F4
SRST
F3
0
–
DPS
F0
02h
F2
F1
B*
B register
F0h
00h
Comparator 1 control
register
1
CMP1#
ACh
–
–
–
–
CE1
CE2
CP1
CP2
CN1
CN2
OE1
OE2
CO1
CO2
CMF1 00h
CMF2 00h
00h
Comparator 2 control
register
1
CMP2#
DIVM#
ADh
95h
CPU clock divide-by-M
control
DPTR:
DPH
Data pointer (2 bytes)
Data pointer high byte
Data pointer low byte
83h
82h
00h
00h
DPL
CF
CE
CD
0
CC
TIRUN
TIRUN
DC
ARL
CARL
0
CB
–
CA
–
C9
CT1
CT1
D9
C8
2
1
I2CFG#*
I C configuration register
C8h/RD SLAVEN MASTRQ
CT0
CT0
D8
00h
C8h/WR SLAVEN MASTRQ CLRTI
–
–
DF
RDAT
CXA
RDAT
XDAT
AF
DE
ATN
IDLE
0
DD
DRDY
CDR
0
DB
STR
CSTR
0
DA
2
1
MASTER
XSTR
0
I2CON#*
I2DAT#
I C control register
D8h/RD
D8h/WR
D9h/RD
D9h/WR
STP
CSTP
0
–
80h
80h
XSTP
0
2
I C data register
x
x
x
x
x
x
x
AE
AD
AC
ES
AB
ET1
EB
–
AA
A9
A8
IEN0*
Interrupt enable 0
Interrupt enable 1
A8h
E8h
EA
EWD
EE
EBO
ED
EX1
EA
ET0
E9
EX0
E8
00h
00h
00h
EF
EC
–
1
IEN1#*
ETI
BF
–
EC1
BD
EC2
BA
EKB
B9
EI2
B8
BE
BC
PS
BB
PT1
PT1H
FB
–
1
1
IP0*
Interrupt priority 0
B8h
B7h
–
PWD
PWDH
FE
PBO
PBOH
FD
PX1
PX1H
FA
PT0
PT0H
F9
PX0
IP0H#
Interrupt priority 0 high byte
–
PSH
FC
PX0H 00h
F8
FF
1
IP1*
Interrupt priority 1
F8h
F7h
86h
PTI
PTIH
–
PC1
PC1H
–
PC2
PC2H
PKB
PKBH
PI2
00h
00h
00h
1
IP1H#
KBI#
Interrupt priority 1 high byte
Keyboard Interrupt
–
–
–
PI2H
87
T1
86
CMP1
96
85
84
83
CIN1B
93
82
CIN2A
92
81
CIN2B
91
80
P0*
P1*
Port 0
Port 1
80h
90h
CMPREF CIN1A
CMP2 Note 2
90
97
95
RST
A5
–
94
INT1
A4
(P1.7)
A7
(P1.6)
A6
INT0
A3
T0
RxD
A1
TxD
A0
Note 2
A2
P2*
Port 2
A0h
84h
85h
91h
92h
A4h
A5h
87h
–
–
–
–
–
X1
X2
Note 2
P0M1#
P0M2#
P1M1#
P1M2#
P2M1#
P2M2#
PCON
Port 0 output mode 1
Port 0 output mode 2
Port 1 output mode 1
Port 1 output mode 2
Port 2 output mode 1
Port 2 output mode 2
Power control register
(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) 00h
(P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00H
1
(P1M1.7) (P1M1.6)
(P1M2.7) (P1M2.6)
–
–
(P1M1.4)
(P1M2.4)
ENCLK
–
–
–
–
–
(P1M1.1) (P1M1.0) 00h
(P1M2.1) (P1M2.0) 00h
(P2M1.1) (P2M1.0) 00h
(P2M2.1) (P2M2.0) 00h
1
P2S
–
P1S
–
P0S
–
T1OE
–
T0OE
–
1
SMOD1 SMOD0
BOF
POF
GF1
GF0
PD
IDL
Note 3
6
2001 Oct 26
NXP [ NXP ]
