Philips Semiconductors
Preliminary data
Low power, low price, low pin count (20 pin)
microcontroller with 4 kbyte OTP
87LPC764
Bit Functions and Addresses
SFR
Address
Reset
Value
Name
Description
MSB
D7
LSB
D0
P
D6
AC
D5
F0
D4
D3
D2
D1
F1
PSW*
Program status word
D0h
F6h
CY
RS1
RS0
OV
00h
00h
PT0AD#
Port 0 digital input disable
9F
9E
9D
9C
9B
9A
99
TI
98
RI
SCON*
SBUF
Serial port control
98h
99h
SM0
SM1
SM2
REN
TB8
RB8
00h
xxh
Serial port data buffer
register
SADDR# Serial port address register
A9h
B9h
81h
00h
00h
07h
SADEN#
SP
Serial port address enable
Stack pointer
8F
8E
8D
8C
8B
8A
89
88
TCON*
TH0
Timer 0 and 1 control
Timer 0 high byte
Timer 1 high byte
Timer 0 low byte
88h
8Ch
8Dh
8Ah
8Bh
89h
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00h
00h
00h
00h
00h
00h
TH1
TL0
TL1
Timer 1 low byte
TMOD
Timer 0 and 1 mode
GATE
–
C/T
–
M1
M0
GATE
C/T
M1
M0
WDOVF
WDCON# Watchdog control register
WDRST# Watchdog reset register
A7h
A6h
WDRUN WDCLK
WDS2
WDS1
WDS0 Note 4
xxh
NOTES:
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1. Unimplemented bits in SFRs are X (unknown) at all times. Ones should not be written to these bits since they may be used for other
purposes in future derivatives. The reset value shown in the table for these bits is 0.
2. I/O port values at reset are determined by the PRHI bit in the UCFG1 configuration byte.
3. The PCON reset value is x x BOF POF–0 0 0 0b. The BOF and POF flags are not affected by reset. The POF flag is set by hardware upon
power up. The BOF flag is set by the occurrence of a brownout reset/interrupt and upon power up.
4. The WDCON reset value is xx11 0000b for a Watchdog reset, xx01 0000b for all other reset causes if the watchdog is enabled, and xx00
0000b for all other reset causes if the watchdog is disabled.
7
2001 Oct 26
NXP [ NXP ]
