Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
8XC54/58
8XC51FA/FB/FC/80C51FA
8XC51RA+/RB+/RC+/RD+/80C51RA+
Table 2.
SYMBOL
8XC51FA/FB/FC, 8XC51RA+/RB+/RC+/RD+ Special Function Registers
(Continued)
DESCRIPTION
DIRECT
ADDRESS
D0H
CBH
CAH
A9H
B9H
99H
9F
9E
SM1
8E
TR1
CE
EXF2
–
9D
SM2
8D
TF0
CD
RCLK
–
9C
REN
8C
TR0
CC
TCLK
–
9B
TB8
8B
IE1
CB
EXEN2
–
9A
RB8
8A
IT1
CA
TR2
–
99
TI
89
IE0
C9
C/T2
T2OE
98
RI
88
IT0
C8
CP/RL2
DCEN
00H
xxxxxx00B
00H
00H
00H
00H
00H
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
00H
00H
07H
8F
TF1
CF
98H
81H
88H
SM0/FE
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION
MSB
LSB
D7
D6
AC
D5
F0
D4
RS1
D3
RS0
D2
OV
D1
–
D0
P
CY
RESET
VALUE
000000x0B
00H
00H
00H
00H
xxxxxxxxB
PSW*
RACAP2H#
RACAP2L#
SADDR#
SADEN#
SBUF
SCON*
SP
TCON*
Program Status Word
Timer 2 Capture High
Timer 2 Capture Low
Slave Address
Slave Address Mask
Serial Data Buffer
Serial Control
Stack Pointer
Timer Control
T2CON*
T2MOD#
TH0
TH1
TH2#
TL0
TL1
TL2#
TMOD
WDTRST
Timer 2 Control
Timer 2 Mode Control
Timer High 0
Timer High 1
Timer High 2
Timer Low 0
Timer Low 1
Timer Low 2
Timer Mode
C8H
C9H
8CH
8DH
CDH
8AH
8BH
CCH
89H
TF2
–
HDW Watchdog
0A6H
Timer Reset (RX+ only)
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
– Reserved bits.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
CC
and RST must come up at the same time for a proper start-up.
Ports 1, 2, and 3 will asynchronously be driven to their reset
condition when a voltage above V
IH1
(min.) is applied to RESET.
2000 Aug 07
12
PHILIPS [ NXP SEMICONDUCTORS ]
