ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 27: Control bits for IDE-specified DMA transfers…continued
Control bits Description
DMA Hardware register (see Table 35 and Table 36)
MASTER set to logic 0
MDMA read/write (opcode = 06H/07H)
DMA Configuration register (see Table 33 and Table 34)
DMA_MODE[1:0]
ATA_MODE
selects the MDMA mode; timings are ATA(PI) compatible
set to logic 1 (ATA transfer)
DMA Hardware register (see Table 35 and Table 36)
MASTER set to logic 0
UDMA read/write (opcode = 02H/03H)
DMA Configuration register (see Table 33 and Table 34)
DMA_MODE[1:0]
IGNORE_IORDY
ATA_MODE
selects the UDMA mode; timings are ATA(PI) compatible
used to ignore the IORDY pin during transfer
set to logic 1 (ATA transfer)
DMA Hardware register (see Table 35 and Table 36)
MASTER set to logic 0
Remark: The DMA bus defaults to three-state, until a DMA command is executed. All
the other control signals are not three-stated.
9.4.1 DMA Command register (address: 30H)
The DMA Command register is a 1-byte register that initiates all DMA transfer activity
on the DMA Controller. The register is write-only: reading it will return FFH.
Remark: The DMA bus will be in three-state until a DMA command is executed.
Table 28: DMA Command register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Reset
DMA_CMD[7:0]
FFH
FFH
W
Bus reset
Access
Table 29: DMA Command register: bit description
Bit
Symbol
Description
7:0
DMA_CMD[7:0] DMA command code, see Table 30.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
30 of 79
NXP [ NXP ]
