HEF4094B
NXP Semiconductors
8-stage shift-and-store register
t
W
V
I
90 %
90 %
negative
pulse
V
V
V
M
M
10 %
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
90 %
positive
pulse
V
M
M
10 %
10 %
0 V
t
W
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a. Input waveform
V
EXT
V
DD
R
L
V
V
O
I
G
DUT
R
T
C
L
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b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RL = load resistance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 11. Test circuit
Table 10. Test data
Supply voltage Input
VEXT
Load
CL
VDD
VI
tr, tf
tPHL, tPLH
open
tPHZ, tPZH
tPLZ, tPZL
RL
5 V to 15 V
VSS or VDD
20 ns
VSS
VDD
50 pF
1 k
HEF4094B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 11 — 29 August 2013
11 of 20
NXP [ NXP ]
