NXP Semiconductors
HEF4052B
Dual 4-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
HEF4052B
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
V
SS
1
2
3
4
5
6
7
8
001aag215
16 V
DD
HEF4052B
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S1
9
S2
2Y0
2Y2
2Z
2Y3
2Y1
E
V
EE
V
SS
1
2
3
4
5
6
7
8
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16 V
DD
15 1Y2
14 1Y1
13 1Z
12 1Y0
11 1Y3
10 S1
9
S2
Fig 6.
Pin configuration SOT38-4 and SOT109-1
Fig 7.
Pin configuration SOT338-1 and SOT403-1
6.2 Pin description
Table 2.
Symbol
E
V
EE
V
SS
S1, S2
1Z, 2Z
V
DD
Pin description
Pin
6
7
8
10, 9
13, 3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
1Y0, 1Y1, 1Y2, 1Y3, 2Y0, 2Y1, 2Y2, 2Y3 12, 14, 15, 11, 1, 5, 2, 4
HEF4052B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 8 — 17 November 2011
5 of 22
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