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HEF4052BP,652 参数 Datasheet PDF下载

HEF4052BP,652图片预览
型号: HEF4052BP,652
PDF下载: 下载PDF文件 查看货源
内容描述: [HEF4052B - Dual 4-channel analog multiplexer/demultiplexer DIP 16-Pin]
分类和应用: 光电二极管
文件页数/大小: 21 页 / 854 K
品牌: NXP [ NXP ]
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HEF4052B  
Nexperia  
Dual 4-channel analog multiplexer/demultiplexer  
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Test data is given in Table 10.  
Definitions:  
DUT = Device Under Test.  
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.  
CL = Load capacitance including test jig and probe.  
RL = Load resistance.  
Fig 16. Test circuit for measuring switching times  
Table 10. Test data  
Input  
Load  
CL  
S1 position  
[1]  
nYn, nZ  
Sn and E tr, tf  
VM  
RL  
tPHL  
tPLH  
tPZH, tPHZ tPZL, tPLZ other  
VEE VDD VEE  
VDD or VEE VDD or VSS 20 ns  
0.5VDD  
50 pF  
10 kVDD or VEE VEE  
[1] For nYn to nZ propagation delays use VEE. For Sn to nYn or nZ propagation delays use VDD  
.
HEF4052B  
All information provided in this document is subject to legal disclaimers.  
©
Nexperia B.V. 2017. All rights reserved  
Product data sheet  
Rev. 10 — 25 March 2016  
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