Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
VDD
V
SYMBOL MIN.
TYP.
MAX.
VCO
Operating supply
voltage
VDD
3
5
15
15
V
as fixed oscillator only
V
phase-locked loop operation
Power dissipation
5
150
2500
µW
µW
µW
MHz
MHz
MHz
%/°C
%/°C
%/°C
%/°C
%/°C
%/°C
%
fo = 10 kHz; R1 = 1 MΩ;
10 P
R2 = ∞; VCOIN at 1⁄2 VDD
;
see also Figs 10 and 11
15
9000
Maximum operating
frequency
5
0,5
1,0
1,3
1,0
VCOIN at VDD
;
10 fmax
2,0
R1 = 10 kΩ; R2 = ∞;
C1 = 50 pF
15
5
2,7
Temperature/
frequency
stability
0,22 0,30
0,04 0,05
0,01 0,05
no frequency offset
(fmin = 0);
see also note 1
10
15
5
0
0
0
0,22
0,04
0,01
with frequency offset
(fmin > 0);
see also note 1
10
15
5
Linearity
0,50
R1 > 10 kΩ
R1 > 400 kΩ
R1 = 1 MΩ
see Fig.13
and Figs 14
15 and 16
10
15
5
0,25
0,25
50
%
%
Duty factor at
VCOOUT
%
10 δ
15
5
50
%
50
%
Input resistance at
VCOIN
106
106
106
MΩ
MΩ
MΩ
10 RIN
15
Source follower
Offset voltage
VCOIN minus
SFOUT
5
10
15
5
1,7
2,0
2,1
1,5
1,7
1,8
0,3
1,0
1,3
V
RSF = 10 kΩ;
V
VCOIN at 1⁄2 VDD
V
V
RSF = 50 kΩ;
VCOIN at 1⁄2 VDD
10
15
5
V
V
Linearity
%
%
%
R
SF > 50 kΩ;
10
15
see Fig.13
Zener diode
Zener voltage
VZ
RZ
7,3
25
V
IZ = 50 µA
Dynamic resistance
Ω
IZ = 1 mA
Notes
1. Over the recommended component range.
January 1995
8
NXP [ NXP ]
