Philips Semiconductors
Product specification
HEF4017B
MSI
5-stage Johnson counter
VDD
V
TYPICAL EXTRAPOLATION
FORMULA
SYMBOL MIN.
TYP.
MAX.
Output transition
times
5
10
15
5
60
30
20
60
30
20
120
60
ns
ns
ns
ns
ns
ns
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
10 ns + (1,0 ns/pF) CL
9 ns + (0,42 ns/pF) CL
6 ns + (0,28 ns/pF) CL
HIGH to LOW
tTHL
40
120
60
LOW to HIGH
10
15
tTLH
40
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns
VDD
V
SYMBOL
MIN.
TYP.
MAX.
Hold times
CP0 →CP1
5
90
40
20
80
40
30
45
20
10
40
20
10
ns
ns
ns
ns
ns
ns
10
15
5
thold
CP1 → CP0
10
15
thold
Minimum clock
pulse width:
5
10
15
5
80
40
30
50
30
20
60
30
20
6
40
20
15
25
15
10
30
15
10
12
24
30
ns
tWCPL
tWCPH
=
CP0 = LOW;
ns
see also waveforms
Figs 4 and 5
CP1 = HIGH
ns
Minimum MR
pulse width; HIGH
ns
10
15
5
tWMRH
tRMR
fmax
ns
ns
Recovery time
for MR
ns
10
15
5
ns
ns
Maximum clock
pulse frequency
MHz
MHz
MHz
10
15
12
15
VDD
V
TYPICAL FORMULA FOR P (µW)
2
Dynamic power
dissipation per
package (P)
5
10
15
500 fi + ∑ (foCL) × VDD
where
2
2200 fi + ∑ (foCL) × VDD
fi = input freq. (MHz)
fo = output freq. (MHz)
CL = load cap. (pF)
∑ (foCL) = sum of outputs
2
6000 fi + ∑ (foCL) × VDD
V
DD = supply voltage (V)
January 1995
5
NXP [ NXP ]
