Philips Semiconductors
Product specification
N-channel vertical D-MOS transistor
DESCRIPTION
N-channel enhancement mode
vertical D-MOS transistor in TO-92
variant envelope and intended for use
in relay, high-speed and
line-transformer drivers.
FEATURES
•
Very low R
DS(on)
.
•
Direct interface to C-MOS, TTL,
etc.
•
High-speed switching.
•
No secondary breakdown.
PINNING - TO-92 VARIANT
1 = source
2 = gate
3 = drain
PIN CONFIGURATION
QUICK REFERENCE DATA
Drain-source voltage
Gate-source voltage
Drain current (DC)
Total power dissipation up to T
amb
= 25
°C
Junction temperature
Drain-source ON-resistance
V
GS
= 10 V; I
D
= 200 mA
R
DS(on)
max.
V
DS
V
GS
I
D
P
tot
T
j
max.
max.
max.
max.
max.
BS170
60 V
15 V
500 mA
830 mW
150
°C
5
Ω
handbook, halfpage
d
1
2
3
g
MAM146
s
Note:
Various pin configurations available.
Fig.1 Simplified outline and symbol.
April 1995
2
PHILIPS [ NXP SEMICONDUCTORS ]
