Philips Semiconductors
Product data
CMOS 8-bit A/D converters
ADC0803/0804
3-STATE TEST CIRCUITS AND WAVEFORMS (ADC0801-1)
20ns
V
CC
V
CC
RD
CS
C
L
10 pF
DATA
OUTPUT
10 kΩ
RD
GND
V
OH
DATA
OUTPUT GND
t
r
90%
50%
10%
t
1H
90%
RD
CS
C
L
V
CC
V
CC
V
CC
RD
10 kΩ
DATA
OUTPUT
10 pF
GND
V
OH
DATA
OUTPUT GND
t
r
90%
50%
10%
t
0H
10%
t
1H
t
OH
SL00019
Figure 4. 3-State Test Circuits and Waveforms (ADC0801-1)
TIMING DIAGRAMS
(All timing is measured from the 50% voltage points)
START
CONVERSION
CS
WR
t
WI
t
W(WR)L
”BUSY”
ACTUAL INTERNAL
STATUS OF THE
CONVERTER
INTR
(LAST DATA WAS NOT READ)
INT ASSERTED
1/2 T
CLK
”NOT BUSY”
(LAST DATA WAS READ)
1 TO 8 X 1/f
CLK
INTERNAL T
C
DATA IS VALID IN
OUTPUT LATCHES
INTR
INTR RESET
CS
t
RI
RD
NOTE
DATA
OUTPUTS
t
ACC
t
1H,
t
0H
THREE–STATE
Output Enable and Reset INTR
NOTE:
Read strobe must occur 8 clock periods (8/f
CLK
) after assertion of interrupt to guarantee reset of INTR.
SL00020
Figure 5. Timing Diagrams
2002 Oct 17
10
PHILIPS [ NXP SEMICONDUCTORS ]
