74LVC1G32-Q100
NXP Semiconductors
Single 2-input OR gate
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
1
Description
data input
B
A
2
data input
GND
Y
3
ground (0 V)
data output
supply voltage
4
VCC
5
7. Functional description
Table 4.
Function table[1]
Input
Output
A
L
B
L
Y
L
L
H
L
H
H
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
0.5
50
0.5
-
Max
+6.5
-
Unit
V
supply voltage
input clamping current
input voltage
VI < 0 V
mA
V
[1]
VI
+6.5
50
VCC + 0.5
+6.5
50
100
-
IOK
output clamping current
output voltage
VO > VCC or VO < 0 V
Active mode
mA
V
[1][2]
[1][2]
VO
0.5
0.5
-
Power-down mode
VO = 0 V to VCC
V
IO
output current
mA
mA
mA
mW
C
ICC
IGND
Ptot
Tstg
supply current
-
ground current
100
-
[3]
total power dissipation
storage temperature
Tamb = 40 C to +125 C
250
+150
65
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
74LVC1G32_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
3 of 13
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