74LVC1G32-Q100
NXP Semiconductors
Single 2-input OR gate
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature
range
Name
Description
Version
74LVC1G32GW-Q100 40 C to +125 C TSSOP5
plastic thin shrink small outline package; 5 leads; SOT353-1
body width 1.25 mm
74LVC1G32GV-Q100
40 C to +125 C SC-74A
plastic surface-mounted package; 5 leads
SOT753
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G32GW-Q100
74LVC1G32GV-Q100
VG
V32
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
B
1
2
1
2
B
A
≥1
Y
4
Y
4
A
mna166
mna165
mna164
Fig 1. Logic symbol
Fig 2. IEC logic symbol
Fig 3. Logic diagram
6. Pinning information
6.1 Pinning
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢊꢅꢋꢋ
ꢈ
ꢉ
ꢊ
ꢋ
ꢀ
ꢃ
ꢁ
ꢇ
ꢂꢂ
ꢌ
ꢄꢅꢆ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
Fig 4. Pin configuration SOT353-1 and SOT753
74LVC1G32_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
2 of 13
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