Philips Semiconductors
Product specification
Quad 2-input multiplexer
74LVC157A
FEATURES
•
Wide supply voltage range of 1.2 to 3.6 V
•
In accordance with JEDEC standard no. 8-1A
•
CMOS lower power consumption
•
Direct interface with TTL levels
•
5 Volt tolerant inputs, for interfacing with 5 Volt logic
DESCRIPTION
The 74LVC157A is a high-performance, low-power, Si-gate CMOS
device, superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC157A is a quad 2-input multiplexer which select 4 bits of
data from two sources under the control of a common data select
input (S). The four outputs present the selected data in the true
(non-inverted) form. The enable input (E) is active LOW. When E is
HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all
other input conditions. Moving the data from two groups of registers
to four common output buses is a common use of the 74LV157. The
state of the common data select input (S) determines the particular
register from which the data comes. It can also be used as function
generator.
The device is useful for implementing highly irregular logic by
generating any four of the 16 different functions of two variables with
one variable common.
The 74LVC157A is the logic implementation of a 4-pole, 2-position
switch, where the position of the switch is determined by the logic
levels applied to S.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
nl
0
, nl1, to nY
E to nY
S to nY
Input capacitance
Power dissipation capacitance per gate
V
I
= GND to V
CC1
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
TYPICAL
3.1
3.0
3.3
5.0
33
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)Σ
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacitance in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
Σ
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC157A D
74LVC157A DB
74LVC157A PW
NORTH AMERICA
74LVC157A D
74LVC157A DB
74LVC157APW DH
PKG. DWG. #
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
S
1I
1I
0
1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
E
4I
4I
0
1
PIN DESCRIPTION
PIN
NUMBER
1
2, 5, 11, 14
3, 6, 10, 13
4, 7, 9, 12
8
3I
3I
0
1
SYMBOL
S
1l
0
to 4l
0
1l
1
to 4l
1
1Y to 4Y
GND
E
V
CC
FUNCTION
Common data select input
Data inputs from sources 0
Data inputs from sources 1
Multiplexer outputs
Ground (0 V)
Enable input (active LOW)
Positive supply voltage
1Y
2I
2I
0
1
4Y
15
16
2Y
GND
3Y
SV00563
1998 Jul 29
2
853-1945 19802
PHILIPS [ NXP SEMICONDUCTORS ]
