Philips Semiconductors
Product specification
3-to-8 line decoder/demultiplexer; inverting
74LVC138A
FEATURES
•
Wide supply voltage range of 1.2 to 3.6 V
•
In accordance with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5 V
•
CMOS lower power consumption
•
Direct interface with TTL levels
•
Demultiplexing capability
•
Multiple input enable for easy expansion
•
Ideal for memory chip select decoding
•
Active LOW mutually exclusive outputs
•
Output drive capability 50
W
transmission lines at 85°C
DESCRIPTION
The 74LVC138A is a low-voltage, low-power, high-performance
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
The 74LVC138A accepts three binary weighted address inputs (A
0
,
A
1
, A
2
) and when enabled, provides 8 mutually exclusive active
LOW outputs (Y
0
to Y
7
).
The 74LVC138A features three enable inputs: two active LOW (E
1
and E
2
) and one active HIGH (E
3
). Every output will be HIGH unless
E
1
and E
2
are LOW and E
3
is HIGH.
This multiple enable function allows easy parallel expansion of the
74LV138A to a 1-of-32 (5 lines to 32 lines) decoder with just four
74LV138A ICs and one inverter. The 74LV138A can be used as an
eight output demultiplexer by using one of the active LOW enable
inputs as the data input and the remaining enable inputs as strobes.
Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
An to Yn,
E
3
to Yn, En to Yn
Input capacitance
Power dissipation capacitance per
package
V
CC
= 3.3 V
Notes 1 and 2
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
TYPICAL
3.5
3.5
5.0
44
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
16-Pin Plastic SO
16-Pin Plastic SSOP Type II
16-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC138A D
74LVC138A DB
74LVC138A PW
NORTH AMERICA
74LVC138A D
74LVC138A DB
74LVC138APW DH
PKG. DWG. #
SOT109-1
SOT338-1
SOT403-1
PIN CONFIGURATION
A
0
A
1
A
2
E
1
E
2
E
3
Y
7
1
2
3
4
5
6
7
16
15
14
13
12
11
10
9
V
CC
Y
0
Y
0
Y
0
Y
0
Y
0
Y
0
Y
0
LOGIC DIAGRAM
1
2
3
A
0
A
1
A
2
Y
0
Y
1
Y
2
Y
3
Y
4
4
5
6
E
1
E
2
E
3
Y
5
Y
6
Y
7
15
14
13
12
11
10
9
7
GND 8
SV00553
SV00554
1998 Apr 28
2
853–1943 19308
PHILIPS [ NXP SEMICONDUCTORS ]
