Philips Semiconductors
Product specification
Quad buffer/line driver with 5-volt
tolerant inputs/outputs (3-state)
74LVC125A
FEATURES
•
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•
Supply voltage range of 1.2V to 3.6V
•
Complies with JEDEC standard no. 8-1A
•
CMOS low power consumption
•
Direct interface with TTL levels
•
High impedance when V
CC
= 0V
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
≤
2.5 ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
g
y
nA to nY
Input capacitance
Power dissipation capacitance per buffer
DESCRIPTION
The 74LVC125A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V.
The 74LVC125A consists of four non-inverting buffers/line drivers
with 3-state outputs. The 3-state outputs (nY) are controlled by the
output enable input (nOE). A HIGH at nOE causes the outputs to
assume a high impedance OFF-state.
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
V
CC
= 3.3 V
Notes 1 and 2
TYPICAL
30
3.0
5.0
25
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
OUTSIDE NORTH AMERICA
74LVC125A D
74LVC125A DB
74LVC125A PW
NORTH AMERICA
74LVC125A D
74LVC125A DB
7LVC125APW DH
PKG. DWG. #
SOT108-1
SOT337-1
SOT402-1
1998 Apr 28
2
853-2010 19310
PHILIPS [ NXP SEMICONDUCTORS ]
