Philips Semiconductors
Product specification
Quad 2-input AND gate
74LVC08A
FEATURES
•
Wide supply voltage range of 1.2 V to 3.6 V
•
In accordance with JEDEC standard no. 8-1A
•
Inputs accept voltages up to 5.5 V
•
CMOS low power consumption
•
Direct interface with TTL levels
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25°C; t
r
= t
f
v2.5
ns
SYMBOL
t
PHL
/t
PLH
C
I
C
PD
PARAMETER
Propagation delay
nA, nB to nY
Input capacitance
Power dissipation capacitance per gate
DESCRIPTION
The 74LVC08A is a high-performance, low-power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
The 74LVC08A provides the 2-input AND function.
CONDITIONS
C
L
= 50 pF;
V
CC
= 3.3 V
Notes 1 and 2
TYPICAL
2.6
5.0
28
UNIT
ns
pF
pF
NOTES:
1. C
PD
is used to determine the dynamic power dissipation
(P
D
in
µW)
P
D
= C
PD
×
V
CC2
×
f
i
)
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz; C
L
= output load capacity in pF;
f
o
= output frequency in MHz; V
CC
= supply voltage in V;
(C
L
×
V
CC2
×
f
o
) = sum of the outputs.
2. The condition is V
I
= GND to V
CC.
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP Type II
14-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVC08A D
74LVC08A DB
74LVC08A PW
NORTH AMERICA
74LVC08A D
74LVC08A DB
74LVC08APW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
PIN CONFIGURATION
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
LOGIC SYMBOL
1
2
4
5
9
10
12
13
1A
1B
2A
2B
3A
3B
4A
4B
1Y
3
2Y
6
3Y
8
4Y
11
SY00034
SV00435
PIN DESCRIPTION
PIN NUMBER
1, 4, 9, 12
2, 5, 10, 13
3, 6, 8, 11
7
14
SYMBOL
1A – 4A
1B – 4B
1Y – 4Y
GND
V
CC
Data inputs
Data outputs
Ground (0 V)
Positive supply voltage
NAME AND FUNCTION
1997 Jun 30
2
853-1996 18167
PHILIPS [ NXP SEMICONDUCTORS ]
