74HC595-Q100; 74HCT595-Q100
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6. Pinning information
6.1 Pinning
ꢀꢁꢂꢃꢄꢅꢄꢆꢇꢈꢉꢉ
ꢀꢁꢂꢃꢊꢄꢅꢄꢆꢇꢈꢉꢉ
ꢁ
ꢄ
ꢆ
ꢉ
ꢌ
ꢏ
ꢑ
ꢖ
ꢁꢏ
ꢁꢌ
ꢁꢉ
ꢁꢆ
ꢁꢄ
ꢁꢁ
ꢁꢅ
ꢗ
ꢀꢁ
ꢀꢄ
ꢂ
ꢃꢃ
ꢀꢁꢂꢃꢄꢅꢄꢆꢇꢈꢉꢉ
ꢀꢁꢂꢃꢊꢄꢅꢄꢆꢇꢈꢉꢉ
ꢀꢅ
ꢀꢆ
ꢇꢈ
ꢁ
ꢄ
ꢆ
ꢉ
ꢌ
ꢏ
ꢑ
ꢖ
ꢁꢏ
ꢁꢌ
ꢁꢉ
ꢁꢆ
ꢁꢄ
ꢁꢁ
ꢁꢅ
ꢗ
ꢀꢁ
ꢀꢄ
ꢂ
ꢃꢃ
ꢀꢅ
ꢀꢉ
ꢊꢋ
ꢀꢆ
ꢇꢈ
ꢀꢌ
ꢈꢍꢃꢎ
ꢈꢐꢃꢎ
ꢒꢓ
ꢀꢉ
ꢊꢋ
ꢀꢏ
ꢀꢌ
ꢈꢍꢃꢎ
ꢈꢐꢃꢎ
ꢒꢓ
ꢀꢏ
ꢀꢑ
ꢀꢑ
ꢔꢕꢇ
ꢀꢑꢈ
ꢔꢕꢇ
ꢀꢑꢈ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢅ
Fig 5. Pin configuration SO16
Fig 6. Pin configuration (T)SSOP16
ꢀꢁꢂꢃꢄꢅꢄꢆꢇꢈꢉꢉ
ꢀꢁꢂꢃꢊꢄꢅꢄꢆꢇꢈꢉꢉ
ꢝꢘ&$ꢚꢙ'!ꢁ
$ꢚ(ꢝ)!ꢙꢘꢝꢙ
ꢄ
ꢁꢌ
ꢁꢉ
ꢁꢆ
ꢁꢄ
ꢁꢁ
ꢁꢅ
ꢀꢄ
ꢀꢅ
ꢆ
ꢉ
ꢌ
ꢏ
ꢑ
ꢀꢆ
ꢀꢉ
ꢀꢌ
ꢀꢏ
ꢀꢑ
ꢇꢈ
ꢊꢋ
ꢈꢍꢃꢎ
ꢈꢐꢃꢎ
ꢒꢓ
*ꢁ+
ꢔꢕꢇ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
ꢍꢘꢙꢚꢛꢜꢙꢘꢝꢚ ! "ꢜ!#$ꢝ%
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to
GND.
Fig 7. Pin configuration for DHVQFN16
74HC_HCT595_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 April 2013
4 of 23
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