NXP Semiconductors
74HC30; 74HCT30
8-input NAND gate
5. Pinning information
5.1 Pinning
74HC30
74HCT30
A
B
C
D
E
F
GND
1
2
3
4
5
6
7
001aal790
14 V
CC
13 n.c.
12 H
11 G
10 n.c.
9
8
n.c.
Y
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
5.2 Pin description
Table 2.
Symbol
A
B
C
D
E
F
GND
Y
n.c.
n.c.
G
H
n.c.
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
data input
data input
data input
data input
data input
data input
ground (0 V)
data output
not connected
not connected
data input
data input
not connected
supply voltage
74HC_HCT30
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 6 — 27 December 2012
3 of 16
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