Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
74HC/HCT166
The number of clock pulses required between the tPLH and tPHL
measurements can be determined from the function table.
CE may change only from HIGH-to-LOW while CP is LOW.
The shaded areas indicate when the input is permitted to change for
predictable output performance.
(1) HC : VM = 50%; VI = GND to VCC
HCT: VM = 1.3V; VI = GND to 3V.
.
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds), the data inputs (Dn), the
clock enable input (LOW CE), the clock enable input CE and the parallel enable input to the clock (CP).
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
10
PHILIPS [ PHILIPS SEMICONDUCTORS ]
