Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
FUNCTION TABLE
OPERATING
MODE
asynchronous set
asynchronous reset
undetermined
toggle
load “0” (reset)
load “1” (set)
hold “no change”
Notes
INPUTS
S
D
L
H
L
H
H
H
H
R
D
H
L
L
H
H
H
H
CP
X
X
X
↑
↑
↑
↑
J
X
X
X
h
l
h
l
74HC/HCT109
OUTPUTS
K
X
X
X
l
l
h
h
Q
H
L
H
q
L
H
q
Q
L
H
H
q
H
L
q
Fig.4 Functional diagram.
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time
prior to the LOW-to-HIGH CP transition
X = don’t care
↑
= LOW-to-HIGH CP transition
handbook, full pagewidth
Q
C
K
Q
J
C
C
C
C
C
C
C
S
R
C
CP
C
MBK217
Fig.5 Logic diagram (one flip-flop).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”.
1997 Nov 25
4
PHILIPS [ NXP SEMICONDUCTORS ]
