NXP Semiconductors
74HC02; 74HCT02
Quad 2-input NOR gate
4. Functional diagram
2
1Y
1
3
5
2Y
4
6
8
9
4Y
13
11
12
mna216
2
3
5
6
8
9
11
12
1A
1B
2A
2B
3A
3B
4A
4B
≥1
1
≥1
4
3Y
10
≥1
10
A
Y
B
mna215
≥1
13
001aah084
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
5. Pinning information
5.1 Pinning
terminal 1
index area
1A
1Y
1A
1B
2Y
2A
2B
GND
1
2
3
4
5
6
7
001aac919
2
3
4
5
6
7
GND
3A
8
14 V
CC
13 4Y
12 4B
11 4A
10 3Y
9
3B
14 V
CC
13 4Y
12 4B
1B
2Y
2A
2B
GND
(1)
02
11 4A
10 3Y
9
8
3B
3A
1
1Y
02
001aac920
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 4.
Pin configuration DIP14, SO14 and (T)SSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y to 4Y
1A to 4A
1B to 4B
GND
V
CC
Pin description
Pin
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9,12
7
14
Description
data output
data input
data input
ground (0 V)
supply voltage
74HC_HCT02
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 4 September 2012
2 of 16
PHILIPS [ NXP SEMICONDUCTORS ]
