NXP Semiconductors
74HC02-Q100; 74HCT02-Q100
Quad 2-input NOR gate
3. Ordering information
Table 1.
Ordering information
Package
Temperature range Name
74HC02D-Q100
74HCT02D-Q100
74HC02PW-Q100
74HCT02PW-Q100
74HC02BQ-Q100
74HCT02BQ-Q100
40 C
to +125
C
40 C
to +125
C
TSSOP14
40 C
to +125
C
SO14
Description
plastic small outline package; 14 leads; body width
3.9 mm
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
Version
SOT108-1
SOT402-1
SOT762-1
Type number
DHVQFN14 plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5
3
0.85 mm
4. Functional diagram
2
1Y
1
3
5
2Y
4
6
8
9
4Y
13
11
12
mna216
2
3
5
6
8
9
11
12
1A
1B
2A
2B
3A
3B
4A
4B
≥1
1
≥1
4
3Y
10
≥1
10
A
Y
B
mna215
≥1
13
001aah084
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram (one gate)
74HC_HCT02_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 24 July 2012
2 of 15
PHILIPS [ NXP SEMICONDUCTORS ]
