Philips Semiconductors
Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
handbook, full pagewidth
(1)
V
SH
CP
INPUT
M
t
t
su
su
t
t
h
h
(1)
D
INPUT
V
S
M
(1)
Q ' OUTPUT
7
V
M
MLB196
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
handbook, full pagewidth
(1)
V
MR INPUT
M
t
t
rem
W
(1)
SH
CP
INPUT
V
M
t
PHL
(1)
V
Q ' OUTPUT
M
7
MLB197
(1) HC: VM = 50%; VI = GND to VCC
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay
and the master reset to shift clock (SHCP) removal time.
1998 Jun 04
13
NXP [ NXP ]
