NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
6. Pinning information
6.1 Pinning
74HC595
74HCT595
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aao241
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
Q7S
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
1
2
3
4
5
6
7
8
001aao242
74HC595
74HCT595
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
9
Q7S
Fig 5.
Pin configuration DIP16, SO16
Fig 6.
Pin configuration SSOP16, TSSOP16
74HC595
74HCT595
terminal 1
index area
Q2
Q3
Q4
Q5
Q6
Q7
2
3
4
5
6
7
8
GND
Q7S
9
GND
(1)
16 V
CC
15 Q0
14 DS
13 OE
12 STCP
11 SHCP
10 MR
Q1
1
001aao243
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 7.
Pin configuration for DHVQFN16
74HC_HCT595
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 12 December 2011
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