74HC595-Q100; 74HCT595-Q100
NXP Semiconductors
8-bit serial-in, serial or parallel-out shift register with output latches;
3-state
V
I
SHCP input
GND
V
M
t
1/f
max
su
V
I
STCP input
GND
V
M
t
t
W
t
PHL
PLH
V
OH
V
Qn output
M
V
OL
mna558
Measurement points are given in Table 8.
OL and VOH are typical output voltage levels that occur with the output load.
V
Fig 10. Storage clock to output propagation delays
V
I
V
SHCP input
M
GND
t
t
su
su
M
t
t
h
h
V
I
V
DS input
GND
V
OH
V
Q7S output
M
V
OL
mna560
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. Data set-up and hold times
74HC_HCT595_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 10 April 2013
13 of 23
NXP [ NXP ]
