74HC595-Q100; 74HCT595-Q100
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 2 — 10 April 2013
Product data sheet
1. General description
The 74HC595-Q100; 74HCT595-Q100 are high-speed Si-gate CMOS devices and are pin
compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with
JEDEC standard No. 7A.
The 74HC595-Q100; 74HCT595-Q100 are 8-stage serial shift registers with a storage
register and 3-state outputs. The registers have separate clocks. Data is shifted on the
positive-going transitions of the shift register clock input (SHCP). The data in each register
is transferred to the storage register on a positive-going transition of the storage register
clock input (STCP). If both clocks are connected together, the shift register is always one
clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
Multiple package options
3. Applications
Serial-to-parallel data conversion
Remote control holding register
PHILIPS [ NXP SEMICONDUCTORS ]
