NXP Semiconductors
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
+&4
+&74
WHUPLQDO
LQGH[ DUHD
9
&&
4
4
4
4
4
4
4
4
*1'
/(
2(
'
9
&&
4
4
4
4
4
4
4
4
/(
DDD
+&4
+&74
2(
'
'
'
'
'
'
'
'
'
'
'
'
'
'
'
*1'
DDD
7UDQVSDUHQW WRS YLHZ
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 5.
Pin configuration SO20, SSOP20 and
TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
LE
Q[0:7]
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
latch enable input (active HIGH)
supply voltage
19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
74HC_HCT573_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 5 March 2013
4 of 20
PHILIPS [ NXP SEMICONDUCTORS ]
