74HC573-Q100; 74HCT573-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
V
I
OE input
output
V
M
GND
t
t
PZL
PLZ
V
CC
V
LOW-to-OFF
OFF-to-LOW
M
10%
V
OL
t
t
PZH
PHZ
V
OH
90%
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. Enable and disable times
V
h
LE input
M
t
t
su
su
t
t
h
V
Dn input
M
001aae084
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)
Table 8.
Type
Measurement points
Input
VM
Output
VM
74HC573-Q100
74HCT573-Q100
0.5VCC
1.3 V
0.5VCC
1.3 V
74HC_HCT573_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 5 March 2013
11 of 20
NXP [ NXP ]
