NXP Semiconductors
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
6. Functional description
Table 3.
Function table
Control
OE
Enable and read register (transparent
mode)
Latch and read register
Latch register and disable outputs
L
L
H
LE
H
L
L
Input
Dn
L
H
l
h
l
h
[1]
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
Operating mode
Internal
latches
L
H
L
H
L
H
Output
Qn
L
H
L
H
Z
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
V
O
=
0.5
V to (V
CC
+ 0.5 V)
Min
0.5
-
-
-
-
-
65
Max
+7
20
20
35
+70
70
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
-
For SO20: P
tot
derates linearly with 8 mW/K above 70
C.
For SSOP20 and TSSOP20 packages: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN20 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT573_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 5 March 2013
5 of 20
PHILIPS [ NXP SEMICONDUCTORS ]
