NXP Semiconductors
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
74HC573-Q100
74HCT573-Q100
terminal 1
index area
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
GND(1)
13 Q6
12 Q7
GND 10
LE 11
OE
2
3
4
5
6
7
8
9
1
D0
D1
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20 V
CC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
aaa-003603
74HC573-Q100
74HCT573-Q100
D2
D3
D4
D5
D6
D7
GND 10
aaa-003604
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input
Fig 5.
Pin configuration SO20 and TSSOP20
Fig 6.
Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
D[0:7]
GND
LE
Q[0:7]
V
CC
Pin description
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
20
Description
3-state output enable input (active LOW)
data input
ground (0 V)
latch enable input (active HIGH)
supply voltage
19, 18, 17, 16, 15, 14, 13, 12 3-state latch output
74HC_HCT573_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 16 August 2012
4 of 19
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