Philips Semiconductors
Product specification
16-channel analog
multiplexer/demultiplexer
74HC/HCT4067
The 74HC/HCT4067 are 16-channel analog
FEATURES
multiplexers/demultiplexers with four address inputs (S0 to
S3) , an active LOW enable input (E), sixteen independent
inputs/outputs (Y0 to Y15) and a common input/output (Z).
The ”4067” contains sixteen bidirectional analog switches,
each with one side connected to an independent
input/output (Y0 to Y15) and the other side connected to a
common input/output (Z).
With E LOW, one of the sixteen switches is selected (low
impedance ON-state) by S0 to S3. All unselected switches
are in the high impedance OFF-state. With E HIGH, all
switches are in the high impedance OFF-state,
independent of S0 to S3.
• Low “ON” resistance:
80 Ω (typ.) at VCC = 4.5 V
70 Ω (typ.) at VCC = 6.0 V
60 Ω (typ.) at VCC = 9.0 V
typical “break before make” built-in
• Output capability: non-standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4067 are high-speed Si-gate CMOS
devices and are pin compatible with the “4067” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The analog inputs/outputs (Y0 to Y15, and Z) can swing
between VCC as a positive limit and GND as a negative
limit. VCC to GND may not exceed 10 V.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
HC
HCT
tPZL/ tPZH turn-on time
E to Vos
CL = 15 pF; RL = 1 kΩ; VCC = 5 V
26
32
ns
Sn to Vos
29
33
ns
t
PLZ/ tPHZ turn-off time
E to Vos
27
29
3.5
29
26
30
3.5
29
ns
ns
pF
pF
Sn to Vos
CI
input capacitance
CPD
CS
power dissipation capacitance per switch notes 1 and 2
max. switch capacitance
independent (Y)
common (Z)
5
5
pF
pF
45
45
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ { (CL + CS) × VCC2 × fo} where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ {(CL + CS) × VCC2 × fo} = sum of outputs
CL = output load capacitance in pF
CS = max. switch capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
September 1993
2
NXP [ NXP ]
