Philips Semiconductors
Product specification
Programmable divide-by-n counter
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
SYMBOL
PARAMETER
CONDITIONS
74HC/HCT4059
TYPICAL
HC
HCT
20
40
3.5
32
UNIT
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
propagation delay CP to Q
maximum clock frequency
input capacitance
power dissipation capacitance per package
C
L
= 15 pF; V
CC
= 5 V 18
40
3.5
notes 1 and 2
30
ns
MHz
pF
pF
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
TYPE
NUMBER
74HC4059N3;
74HCT4059N3
74HC4059N;
74HCT4059N
74HC4059D;
74HCT4059D
PACKAGE
NAME
DIP24
DIP24
SO24
DESCRIPTION
plastic dual in-line package; 24 leads (300 mil)
plastic dual in-line package; 24 leads (600 mil)
plastic small outline package; 24 leads; body width 7.5 mm
VERSION
SOT222-1
SOT101-1
SOT137-1
1998 Jul 08
4
PHILIPS [ NXP SEMICONDUCTORS ]
