Philips Semiconductors
Product specification
Programmable divide-by-n counter
74HC/HCT4059
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
HC HCT
UNIT
tPHL/ tPLH
propagation delay CP to Q
maximum clock frequency
input capacitance
CL = 15 pF; VCC = 5 V 18
20
40
3.5
32
ns
fmax
CI
40
MHz
pF
3.5
CPD
power dissipation capacitance per package notes 1 and 2
30
pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
DESCRIPTION
VERSION
74HC4059N3;
74HCT4059N3
DIP24
plastic dual in-line package; 24 leads (300 mil)
SOT222-1
74HC4059N;
74HCT4059N
DIP24
SO24
plastic dual in-line package; 24 leads (600 mil)
SOT101-1
SOT137-1
74HC4059D;
74HCT4059D
plastic small outline package; 24 leads; body width 7.5 mm
1998 Jul 08
4
NXP [ NXP ]
